A solid state drive (SSD) is designed to provide reliable and high performance storage of user data across a flash-based memory system containing a host interface controller (such as a Serial Advanced Technology Attachment (SATA)) interface) and a number of memory multi-chip packages (MCPs), where each MCP contains a flash memory controller and a stack of NAND flash dies. The Open NAND Flash Interface (ONFI) protocol provides support for parallel access to multiple NAND dies (or “logical units” (LUNs)) on a single “target” or NAND multi-chip stack on a single shared ONFI channel. In a typical SATA-based SSD application, a central host controller accesses multiple attached devices (targets/NAND device clusters) on each ONFI channel, and across several ONFI channels. Each ONFI target typically controls 2, 4, or 8 NAND dies. Storage management software running on the host controller manages a virtual memory space that is mapped to flash blocks in the physical dies in each of the attached MCP's. The host controller and the storage management software utilize parallel access and efficient usage of the available flash devices to optimize SSD drive performance, endurance, and cost. The system often must achieve these optimizations within product-related or technology-related power and thermal limits, which are often set forth in the specifications for the product. For example, in some SSD assemblies, the SSD assembly must not exceed 10 W peak power consumption under any operational mode. As another example, in some MCP packages, the MCP package must not exceed 90 degrees Celsius under any operational scenario.
Different techniques have been used to manage power and case temperature within required limits. For example, the host controller or the storage management software can employ techniques such as load balancing, “hot spot” prevention, and regulating garbage collection activity in order to lower the overall temperature of the device. As another example, the host can employ a host-initiated power management/power-down (HIPM/HIPD) technique in which the host de-powers some number of target modules or directs them to enter a standby/power-down mode. In this way, the host reduces traffic to some number of devices. As yet another example, the storage device can employ a device-initiated power management/power-down (DIPM/DIPD) technique in which the controller within the memory module monitors host activity and incoming commands and, if a first threshold amount of time passes with no activity, the controller can reduce its clocks and/or power-down some of its sub-modules, such that its response to new commands will be longer or slower. If a second longer threshold amount of time passes with no activity, the controller can possibly enter a low-power standby or sleep mode, in which a small amount of wake-up circuitry remains powered, but responses to new commands will be further increased or slowed.